SerDes compliance analysis in VX.2.12 includes new VEC/VEO Measurements required for 112Gb/s IEEE/OIF: Helpful when screening many links to determine which links need a more detailed investigation.A shorter report is easier to read lists pass/fail status and operating margin.VX.2.12 provides now a shorter report with just the summary information helping to quickly find the signals which might need further attention. VX.2.12 has now the new ability to model controllers to optimize timing Command / Address signals by class or at the individual bit levels. HyperLynx is traditionally able to emulate various controller timing behaviours. Eyes plotted with probabilities in colourĪddress and Command Deskewing within DDR5 Simulations.Works with AMI models & Tx/Rx jitter specs.The complete list of the algorithm’s new and updated features:

HyperLynx Advanced DDRx AMI algorithm raises the accuracy of IBIS-AMI approach in terms of rise/fall asymmetry associated with DDR signals and suggests users simulation results down to the values 1e-16. The DDR5 specification requires 1e-16 probability level, which is not always possible for IBIS or IBIS-AMI models. Generation of a SerDes compliance short reportĭDR5 Eye Diagram Results Prediction to Probability of 1e-16.Additional DDR controller deskewing support.

DDR5 Eye Diagram Results Prediction to Probability of 1e-16.

Sintecs, as an official specialized distributor of HyperLynx, is happy to make you familiar with the latest improvements already available for all the users of HyperLynx SI and PI bundles. The updated package includes, of course, a refreshed set of HyperLynx solutions for signal and power integrity.

Siemens EDA (ex-Mentor Graphics) released days ago a new version of the VX toolset under the index 2.12.

Siemens hyperlynx